FIG. 1 (prior art) is a simplified schematic block diagram of a conventional sigma-delta converter (SD converter) 10. SD converter 10 includes a sigma-delta modulator (SD modulator) portion 11 and a digital filter 12. SD modulator portion 11 is a first-order modulator and includes a summing amplifier 13, an integrator 14, a clocked comparator 15, and a switching device 16.
SD modulator portion 11 operates in cycles as determined by a clock signal of frequency kfS that clocks comparator 15. Summing amplifier 13 outputs an error signal 19 that represents the difference between an analog input signal 17 and a feedback signal 18. Error signal 19 represents the change in voltage of input signal 17 since the previous cycle of SD modulator portion 11. Integrator 14 performs a time domain integration of error signal 19, yielding an integrated analog output signal 20. Clocked comparator 15 compares analog output signal 20 to a fixed voltage (here, zero volts) on its inverting input lead, thereby converting analog output signal 20 into a one-bit data stream 21 having a bit rate equal to the clock rate. This one-bit data stream 21 is supplied to switching device 16. When the value of digital data stream 21 is a digital one, then switching device 16 outputs +5/4 VINmax volts. When the value of digital data stream 21 is a digital zero, then switching device 16 outputs −5/4 VINmax volts. Feedback signal 18 comprising a stream of +5/4 VINmax and −5/4 VINmax values is then fed back to the inverting input lead of summing amplifier 13. The resulting feedback loop of the circuit operates such that a running average of consecutive values of data stream 21 equals the voltage of input signal 17.
SD modulator portion 11 receives an analog input signal 17 whereas it outputs digital data values, each having a limited number of bits. Thus, some information is lost in the analog-to-digital conversion. Random “quantization noise” is therefore said to be introduced. By oversampling analog input signal 17 at a clock frequency kfS that is much higher than the frequency bandwidth of input signal 17, the quantization noise is spread over a wide frequency range. The magnitude of the quantization noise in the frequency band of interest is therefore decreased.
Integrator 14 operates further to reduce the magnitude of quantization noise in the frequency band of interest. Integrator 14 acts as a low-pass filter to the input signal 17 and as a high-pass filter to the quantization noise. The quantization noise is therefore “shaped” by integrator 14 and is pushed into higher frequencies.
The digital data stream 21 as output by SD modulator portion 11 is then filtered by digital filter 12. Filtering reduces the data rate of digital data stream 21. Filtering also removes most of the quantization noise that has been shaped into higher frequencies.
The SD converter 10 of FIG. 1 outputs a data stream of one-bit values. This example provides a simple description of the operation of a SD converter. There are, however, other SD converters that output data streams of multi-bit values.
FIG. 2 (prior art) is a graph illustrative of the output of such an SD converter that outputs a stream of three-bit values. The largest three-bit value is “111” as indicated by the top three-bit value in the column labeled “8 digital states”. The smallest three-bit value is “000” as indicated by the bottom value in the column labeled “8 digital states”. The stream of three-bit values that corresponds to analog input signal 17 is shown in the top row of the table below the graph.
In addition to the above-described random quantization noise introduced by interpreting a continuous analog input as a discrete digital state, non-random quantization noise is also created. This non-random noise is generated when the SD modulator portion is outputting values near the digital states that are represented by all ones (for example, “111”) and all zeros (for example, “000”). Random noise results when a given analog input value is sometimes interpreted as a higher digital state and sometimes as a lower digital state. Near the digital state of all ones, however, noise cannot result in a digital state that is higher than the state with all ones. Similarly, near the digital state of all zeros, noise cannot result in a digital state that is lower than all zeros. Quantization noise near these two limits of the available digital states is not partially above and partially below the correct state and is, therefore, not random. The non-random quantization noise is not shaped into higher frequencies to the extent that random quantization noise is shaped.
One conventional method for overcoming the non-random quantization noise that occurs near the limits of the available digital states involves voltage scaling. The positive voltage value and the negative voltage value of feedback signal 18 are scaled, for example, by a factor of five fourths, so that the amplitude of error signal 19 is four fifths of its non-scaled value. Because the voltage of the feedback signal 18 can exceed the maximum voltage input voltage of input signal 17, non-random quantization noise that occurs near the limits of the available digital states can be reduced. The amplitude of analog output signal 20 is thereby reduced by four fifths, and the correct digital state of the maximum amplitude of input signal 17 is made to be a digital state less than all ones. Likewise, the correct digital state of the minimum amplitude of input signal 17 is made to be a digital state greater than all zeros.
In FIG. 2, the rightmost column labeled “6 digital states” shows the number of digital states reduced to six after scaling. After scaling, the maximum and minimum amplitudes of input signal 17 correspond to digital states 110 and 001, respectively, instead of to 111 and 000. The lower row of the table below the graph of FIG. 2 shows a series of 3-bit values of such a data stream 21 proceeding from left to right. For a description of a similar method of conventional scaling, see U.S. Pat. No. 4,851,841.
Accordingly, the prior art scaling technique reduces non-random quantization noise by scaling up feedback signal amplitudes so that maximum and minimum input signal voltages are represented digitally by states that are not the maximum and minimum available digital states. Because quantization noise is increased by decreasing the number of digital states, this scaling technique increases random quantization noise. Moreover, scaling up the amplitude of feedback signal 18 increases power consumption.
An apparatus and a method are sought that decrease quantization noise in the frequency band of interest while using all available digital states.